Semiconductor wafers have a semiconductor base. The semiconductor base can be made from any appropriate material such as single crystal silicon, gallium arsenide, and other semiconductor materials known in the art. Over a surface of the semiconductor base is a dielectric layer. This dielectric layer typically contains silicon dioxide, however, other suitable dielectric layers are also contemplated in the art.
Over the front surface of the dielectric layer are numerous discrete metal interconnects (e.g., metal conductor blocks). Each metal interconnect can be made, for example, from aluminum, copper, aluminum copper alloy, tungsten, and the like. These metal interconnects are typically made by first depositing a continuous layer of the metal on the dielectric layer. The metal is then etched and the excess metal removed to form the desired pattern of metal interconnects. Afterwards, an insulating layer is applied over top of each metal interconnect, between the metal interconnects and over the surface of the dielectric layer. The insulating layer is typically a metal oxide such as silicon dioxide, BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), or combinations thereof. The resulting insulating layer often has a front surface that may not be as “planar” and/or “uniform” as desired.
Before any additional layers of circuitry can be applied via a photolithography process, it is desired to treat the front surface of the insulating layer to achieve a desired degree of “planarity” and/or “uniformity;” the particular degree will depend on many factors, including the individual wafer and the application for which it is intended, as well as the nature of any subsequent processing steps to which the wafer may be subjected. For the sake of simplicity, throughout the remainder of this application this process will be referred to as “planarization”. As a result of planarization, the front surface of the insulating layer should be sufficiently planar such that when the subsequent photolithography process is used to create a new circuit design, the critical dimension features can be resolved. These critical dimension features form the circuitry design.
Other layers may also be planarized in the course of the wafer fabrication process. In fact, after each additional layer of insulating material is applied over the metal interconnects, planarization may be needed. The blank wafer may need to be planarized as well. Additionally, the wafer may include conductive layers, such as copper, that need planarization as well. A specific example of such a process is the metal Damascene processes.
In the Damascene process, a pattern is etched into an oxide dielectric (e.g., silicon dioxide) layer. After etching, optional adhesion/barrier layers are deposited over the entire surface. Typical barrier layers may comprise tantalum, tantalum nitride, titanium or titanium nitride, for example. Next, a metal (e.g., copper) is deposited over the dielectric and any adhesion/barrier layers. The deposited metal layer is then modified, refined or finished by removing the deposited metal and optionally portions of the adhesion/barrier layer from the surface of the dielectric. Typically, enough surface metal is removed so that the outer exposed surface of the wafer comprises both metal and an oxide dielectric material. A top view of the exposed wafer surface would reveal a planar surface with metal corresponding to the etched pattern and dielectric material adjacent to the metal. The metal(s) and oxide dielectric material(s) located on the modified surface of the wafer inherently have different physical characteristics, such as different hardness values. The abrasive treatment used to modify a wafer produced by the Damascene process must be designed to simultaneously modify the metal and dielectric materials without scratching the surface of either material. The abrasive treatment creates a planar outer exposed surface on a wafer having an exposed area of a metal and an exposed area of a dielectric material.
One conventional method of modifying or refining exposed surfaces of structured wafers treats a wafer surface with a slurry containing a plurality of loose abrasive particles dispersed in a liquid. Typically this slurry is applied to a polishing pad and the wafer surface is then ground or moved against the pad in order to remove material from the wafer surface. The slurry may also contain chemical agents or working liquids that react with the wafer surface to modify the removal rate. The above described process is commonly referred to as a chemical-mechanical planarization (CMP) process.
An alternative to CMP slurry methods uses an abrasive article to modify or refine a semiconductor surface and thereby eliminate the need for the foregoing slurries. The abrasive article generally includes a sub-pad construction. Examples of such abrasive articles can be found in U.S. Pat. Nos. 5,958,794; 6,194,317; 6,234,875; 5,692,950; and 6,007,407, which are incorporated by reference. The abrasive article has a textured abrasive surface which includes abrasive particles dispersed in a binder. In use, the abrasive article is contacted with a semiconductor wafer surface, often in the presence of a working liquid, with a motion adapted to modify a single layer of material on the wafer and provide a planar, uniform wafer surface. The working liquid is applied to the surface of the wafer to chemically modify or otherwise facilitate the removal of a material from the surface of the wafer under the action of the abrasive article.
The planarization process may be achieved in more than one step. It has been known to planarize a semiconductor wafer in two steps. Generally, it has been known to use a fixed abrasive article with a sub pad in a two step process. Such a fixed abrasive product is described, for example, in U.S. Pat. No. 5,692,950 (Rutherford, et al.), incorporated by reference.